1. Field of the Invention
The present invention relates to a semiconductor device and, more specifically, to a semiconductor device including a variable delay circuit to generate an internal clock signal.
2. Description of Related Art
A semiconductor device such as a DRAM (Dynamic Random Access Memory) may include a clock generating circuit that generates an internal clock signal controlled in phase. As a typical clock generating circuit, a DLL (Delay Locked Loop) circuit is known as a clock adjustment circuit. The DLL circuit has a variable delay circuit that delays an external clock signal to generate an internal clock signal.
In the DLL circuit, a time taken for an initial operation may be problematic. This is because, in the initial operation, since the phase of an internal clock signal largely changes, a relatively long time is taken until the internal clock signal is locked. The term “locked” means a state in which the internal clock signal is correctly controlled in phase. As a method for solving the problem, a method of directly measuring a phase difference with an oscillator is proposed (Japanese Patent Application Laid Open No. 211-9922).